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Dr. Heranmoy Maity

Assistant Professor

  •   PhD

Dr. Heranmoy Maity earned his PhD from the National Institute of Technology Durgapur, India in 2021 and he obtained his M.Tech degree in Electronics and Communication Engineering from Kalyani Govt. Engineering College in Kalyani, West Bengal, India in in 2010. His teaching experience is around 15 years.

Currently, Dr. Maity holds the position of an assistant professor in the Department of Computer Science and Engineering at Symbiosis Institute of Technology, Nagpur, under the Symbiosis International University in Pune, India. His academic journey has been extensive and illustrious, highlighted by an impressive portfolio that includes more than 20 research papers and 6 patents. Dr. Maity's research interests are Quantum Computing, Reversible Logic Design, Digital System Design, Antenna Technology, and Electronic Devices and Circuits.

  • BEEE
  • DELD
  • Specialization
    1. Quantum Computing
  • Focus
    1. Reversible Computing

Journal

No. Information
1 H. Maity et al., “A New Approach to Design of Cost-Efficient Reversible Quantum Dual-Full Adder and Subtractor”. International Journal of Mathematical, Engineering and Management Sciences, 9(2), 341-351 (2024) (Scopus, WoS).
2 H. Maity, “Design and Implementation of Two-Qubit Quantum Comparator Circuit or Q-CC”, Journal of Computational Electronics, Vol. 21(2), pp. 530-534 (2022).
3 H. Maity et al., “Design of BCD to Excess-3 Code Converter Circuit with Optimized Quantum Cost, Garbage Output and Constant Input Using Reversible Gate”, International Journal of Quantum Information, Vol. 16, No. 7 (2018) 1850061 (5 pages).
4 H. Maity et al., “Quantum Cost Optimized Design of 4-bit Reversible Universal Shift Register Using Reduced Number of Logic Gate”, International Journal of Quantum Information, Vol. 16, No. 2 (2018) 1850016 (8 pages).
5 H. Maity et al., “Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter”, Journal of Circuits, System and Computers, Vol. 27, No. 12 (2018) 1850184 (11 pages).
6 H. Maity et al., “Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)”, Micro and Nanosystems, Vol. 13, No. 01, pp. 119-123. (2021).
7 H. Maity et al., “Design and Development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate”, Micro and Nanosystems, Vol. 13, No. 01, pp. 124-127. (2021).
8 H. Maity et al., “The Quantum Cost Optimized Design of 2:4 Decoder Using New Reversible Gate”, Micro and Nanosystems, Vol. 12, No. 02, pp. 146-148, (2020).
9 H. Maity, “A New Approach to Design and Implementation of 2-Input XOR Gate Using 4-Transistor”, Micro and Nanosystems, Vol. 12, No. 03, pp. 240-242, (2020).
10 H. Maity et al., “Design of Reversible Shift Register Using Reduced Number of Logic Gate”, Micro and Nanosystems, Vol. 12, No. 01, pp. 33-37, (2020).
11 H. Maity et al., “Design of Reversible Combinational Circuits Using New Reversible Logic Gate”, Journal of Engineering Science and Technology Review, Vol. 11, No. 5, pp. 170 – 172, (2018).

Conferences

No. Information
1 H. Maity et al., “Input Variable Bypass or IVR Technique for Logic Functions Simplification”, IEEE Int. Conf. on Device for Integrated Circuit (DevIC 2023), Kalyani India, 7-8 April 2023, pp:1-3.
2 H. Maity et al., “Implementation of the Quantum BCD-to-Excess-3 Code Converter using New Quantum Reversible Circuit Block”, IEEE Int. Conf. on Device for Integrated Circuit (DevIC 2023), Kalyani India, 7-8 April 2023, pp:26-29.
3 H. Maity et al., “The Quantum Cost, Garbage Outputs and Constant Input Optimized Implementation of 2:4 Decoder Using Peres Gate”, IEEE Int. Conf. on Device for Integrated Circuit (DevIC 2019), Kalyani India, 23-24 March 2019, pp:9-11.
4 H. Maity et al., “Quantum Cost Optimized Design of Reversible 2’s Complement Code Converter”, 1st 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), Kolkata, India, 24-25 November 2018, pp: 122-125.
5 H. Maity et al., “Design of Quantum Cost Efficient 4-Bit Reversible Universal Shift Register”, IEEE Int. Conf. on Device for Integrated Circuit (DevIC 2017), Kalyani India, 23-24 March 2017, pp: 44-47.
6 H. Maity et al., “Design of 4-Bit Reversible Johnson Counter with Optimized Quantum Cost, Delay, and Number of Gate”, 1st International Conference on Emerging Trends in Engineering and Science (ETES-2018), Lecture Notes in Networks and Systems (Springer), Asansol, India, 23 -24 March 2018, pp: 539-544.
7 H. Maity et al., “Design of quantum cost efficient MOD-8 synchronous UP/DOWN counter using reversible logic gate”, International Conference on Computational Science and Engineering (ICCSE 2016), Kolkata, India, 4-6 November 2016, pp:3 – 6

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